By Rajesh Garg
This ebook is prompted through the demanding situations confronted in designing trustworthy integratedsystems utilizing smooth VLSI methods. The trustworthy operation of built-in Circuits (ICs) has develop into more and more tricky to accomplish within the deep sub-micron (DSM) period. With regularly lowering equipment function sizes, mixed with decrease offer voltages and better working frequencies, the noise immunity of VLSI circuits is reducing alarmingly. therefore, VLSI circuits have gotten extra at risk of noise results corresponding to crosstalk, energy provide adaptations and radiation-induced gentle errors.
This e-book describes the layout of resilient VLSI circuits. It provides algorithms to investigate the damaging results of radiation particle moves and processing adaptations at the electric habit of VLSI circuits, in addition to circuit layout recommendations to mitigate the impression of those problems.
- Describes the cutting-edge within the parts of radiation tolerant circuit layout and approach edition tolerant circuit design;
- Presents analytical techniques to check successfully the severity of electric results of radiation/process diversifications, in addition to ideas to reduce the results because of those problems;
- Distills content material orientated towards nuclear engineers into modern algorithms and methods that may be understood simply and utilized through VLSI designers.
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Extra info for Analysis and Design of Resilient VLSI Circuits: Mitigating Soft Errors and Process Variations
In future technologies, it is expected that the variation in device parameters will continue to be the dominant source of delay variability of a circuit. 4 shows the standard deviation of the threshold voltage of transistors ( VT ) implemented in different technology nodes . As shown in Fig. 4, VT has increased by a factor of 2 for a 45 nm technology compared with a 130 nm process. Note that the absolute value of VT is higher for 130 nm process ( 0:35 V) compared with a 45 nm process ( 0:28 V).
In Chap. 9, a process variation tolerant design approach for combinational circuits is presented, which exploits the fact that random variations can cause a significant mismatch in two identical devices placed next to each other on the die. In this approach, a large gate is implemented using an appropriate number (>1) of smaller gates, whose inputs and outputs are connected to each other in parallel. This parallel connection of smaller gates to form a larger gate is referred to as a parallel gate.
25. H. Chang and S. S. Sapatnekar, “Statistical timing analysis under spatial correlations,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 9, pp. 1467–1482, Sept. 2005. 26. L. He, A. B. Kahng, K. H. Tam, and J. Xiong, “Simultaneous buffer insertion and wire sizing considering systematic CMP variation and random Leff variation,” Proc. of the Intl. Conf. on Computer-Aided Design, vol. 26, no. 5, pp. 845–857, May 2007. 27. K. Cao, S. Dobre, and J. Hu, “Standard cell characterization considering lithography induced variations,” in Proc.